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Rev 0; 6/04
9-Bit I2C Nonvolatile I/O Expander Plus Memory
General Description
The DS4520 is a 9-bit nonvolatile (NV) I/O expander with 64 bytes of NV user memory controlled by an I 2CTMcompatible serial interface. The DS4520 offers users a digitally programmable alternative to hardware jumpers and mechanical switches that are being used to control digital logic nodes. Furthermore, the digital state of each pin can be read through the serial interface. Each I/O pin is independently configurable. The outputs are open drain with selectable pullups. Each output has the ability to sink up to 12mA. Since the device is NV, it powers up in the desired state allowing it to control digital logic inputs immediately on power-up without having to wait for the host CPU to initiate control.
Features
Programmable Replacement for Mechanical Jumpers and Switches Nine NV Input/Output Pins 64-Byte NV User Memory (EEPROM) I2C-Compatible Serial Interface Up to 8 Devices Can be Multidropped on the Same I2C Bus Open-Drain Outputs with Configurable Pullups Outputs Capable of Sinking 12mA Low Power Consumption Wide Operating Voltage (2.7V to 5.5V) Operating Temperature Range: -40C to +85C
DS4520
Applications
RAM-Based FPGA Bank Switching for Multiple Profiles Selecting Between Boot Flash Setting ASIC Configurations/Profiles Servers Network Storage Routers Telecom Equipment PC Peripherals
Ordering Information
PART DS4520E TEMP RANGE -40C to +85C PIN-PACKAGE 16 TSSOP
Add "/T&R" for tape and reel orders.
Typical Operating Circuit
VCC
Pin Configuration
TOP VIEW
I/O_0 1 16 GND 15 I/O_8 14 I/O_7
0.1F 4.7k FROM SYSTEM CONTROLLER 4.7k
VCC
DS4520
I/O_0 I/O_1 I/O_2 I/O_3 I/O_4 I/O_5 I/O_6 I/O_7 I/O_8 FPGA
I/O_1 2 I/O_2 3 I/O_3 4
CLOCK GENERATOR CPU SPEED SELECT
SCL SDA A0 A1 A2 GND
DS4520
13 I/O_6 12 I/O_5 11 A2 10 SCL 9 SDA
I/O_4 5 A0 6 A1 7 VCC 8
I2C is a trademark of Philips Corp. Purchase of I2C components from Maxim Integrated Products, Inc., or one of its sublicensed Associated Companies, conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
______________________________________________ Maxim Integrated Products
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9-Bit I2C Nonvolatile I/O Expander Plus Memory DS4520
ABSOLUTE MAXIMUM RATINGS
Voltage on VCC, SDA, and SCL Pins Relative to Ground.............................................-0.5V to +6.0V Voltage on A0, A1, A2, and I/O_n [n = 0 to 8] Relative to Ground....-0.5V to (VCC + 0.5V) not to exceed +6.0V Operating Temperature Range ...........................-40C to +85C EEPROM Programming Temperature Range .........0C to +70C Storage Temperature Range .............................-55C to +125C Soldering Temperature ...See IPC/JEDEC J-STD-020A Specification
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED DC OPERATING CONDITIONS
(TA = -40C to +85C)
PARAMETER Supply Voltage Input Logic 1 Input Logic 0 SYMBOL VCC VIH VIL (Note 1) CONDITIONS MIN +2.7 0.7 x VCC -0.3 TYP MAX +5.5 VCC + 0.3 0.3 x VCC UNITS V V V
DC ELECTRICAL CHARACTERISTICS
(VCC = +2.7V to +5.5V; TA = -40C to +85C, unless otherwise noted.)
PARAMETER Standby Current Input Leakage Input Current each I/O Pin Low-Level Output Voltage (SDA) I/O Pin Low-Level Output Voltage I/O Pin Pullup Resistors I/O Capacitance Power-On Reset Voltage SYMBOL ISTBY IL II/O VOL SDA VOL I/O RPU CI/O VPOR (Note 4) 1.6 0.4V < VI/O < 0.9VCC (Note 3) 3mA sink current 6mA sink current 12mA sink current 4.0 5.5 (Note 2) -1.0 -1.0 0 0 CONDITIONS MIN TYP 2 MAX 10 +1.0 +1.0 0.4 0.6 0.4 7.5 10 UNITS A A A V V k pF V
2
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9-Bit I2C Nonvolatile I/O Expander Plus Memory
AC ELECTRICAL CHARACTERISTICS (See Figure 2)
(VCC = +2.7V to +5.5V; TA = -40C to +85C, unless otherwise noted. Timing referenced to VIL(MAX) and VIH(MIN).)
PARAMETER SCL Clock Frequency Bus Free Time Between Stop and Start Conditions Hold Time (Repeated) Start Condition Low Period of SCL High Period of SCL Data Hold Time Data Setup Time Start Setup time SDA and SCL Rise Time SDA and SCL Fall Time Stop Setup Time SDA and SCL Capacitive Loading EEPROM Write Time SYMBOL fSCL tBUF tHD:STA tLOW tHIGH tHD:DAT tSU:DAT tSU:STA tR tF tSU:STO CB tWR (Note 6) (Note 7) 10 (Note 6) (Note 6) (Note 5) CONDITIONS MIN 0 1.3 0.6 1.3 0.6 0 100 0.6 20 + 0.1CB 20 + 0.1CB 0.6 400 20 300 300 0.9 TYP MAX 400 UNITS kHz s s s s s ns s ns ns s pF ms
DS4520
NONVOLATILE MEMORY CHARACTERISTICS
(VCC = +2.7V to +5.5V, unless otherwise noted.)
PARAMETER EEPROM Writes SYMBOL CONDITIONS +70C (Note 4) MIN 50,000 TYP MAX UNITS
Note 1: All voltages referenced to ground. Note 2: ISTBY is specified with SDA = SCL = VCC, outputs floating, and inputs connected to VCC or GND. Note 3: The DS4520 does not obstruct the SDA and SCL lines if VCC is switched off as long as the voltages applied to these inputs do not violate their minimum and maximum input voltage levels. Note 4: Guaranteed by design. Note 5: Timing shown is for fast-mode (400kHz) operation. This device is also backward compatible with I2C standard-mode timing. Note 6: CB--total capacitance of one bus line in picofarads. Note 7: EEPROM write time applies to all the EEPROM memory and SRAM shadowed EEPROM memory when SEE = 0. The EEPROM write time begins after a stop condition occurs.
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9-Bit I2C Nonvolatile I/O Expander Plus Memory DS4520
Typical Operating Characteristics
(VCC = +5.0V, TA = +25C, unless otherwise noted.)
SUPPLY CURRENT vs. SUPPLY VOLTAGE
DS4520 toc01
SUPPLY CURRENT vs. TEMPERATURE
I/O0-I/O7 CONTROL BITS = 0 I/O0-I/O7 PULLUPS DISABLED VCC = SDA = SCL = 5V
DS4520 toc02
2.0 I/O0-I/O7 CONTROL BITS = 0 I/O0-I/O7 PULLUPS DISABLED VCC = SDA = SCL SUPPLY CURRENT (A) 1.5
2.5
2.0 SUPPLY CURRENT (A)
1.5
1.0
1.0
0.5
0.5
0 3.0 3.5 4.0 4.5 5.0 SUPPLY VOLTAGE (V)
0 -40 -20 0 20 40 60 80 TEMPERATURE (C)
SUPPLY CURRENT vs. SCL FREQUENCY
DS4520 toc03
I/O OUTPUT VOLTAGE vs. SUPPLY VOLTAGE
PULLUPS ENABLED PULLDOWNS DISABLED
DS4520 toc04
20 18 16 SUPPLY CURRENT (A) 14 12 10 8 6 4 2 0 0 100 200 300 VCC = SDA = 5V
6 5 I/O VOLTAGE (V) 4 3 HIGH IMPEDANCE 2 EEPROM RECALL AT VPOR 1 0 0 1 2 3 4 5 6 SUPPLY VOLTAGE (V)
400
SCL FREQUENCY (kHz)
4
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9-Bit I2C Nonvolatile I/O Expander Plus Memory
Pin Description
PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 NAME I/O_0 I/O_1 I/O_2 I/O_3 I/O_4 A0 A1 VCC SDA SCL A2 I/O_5 I/O_6 I/O_7 I/O_8 GND Input/Output 0. Bidirectional I/O pin. Input/Output 1. Bidirectional I/O pin. Input/Output 2. Bidirectional I/O pin. Input/Output 3. Bidirectional I/O pin. Input/Output 4. Bidirectional I/O pin. I2C Address Input. Inputs A0, A1, and A2 determine the I2C slave address of the device. I2C Address Input. Inputs A0, A1, and A2 determine the I2C slave address of the device. Power-Supply Voltage I2C Serial Data Open-Drain Input/Output I2C Serial Clock Input I2C Address Input. Inputs A0, A1, and A2 determine the I2C slave address of the device. Input/Output 5. Bidirectional I/O pin. Input/Output 6. Bidirectional I/O pin. Input/Output 7. Bidirectional I/O pin. Input/Output 8. Bidirectional I/O pin. Ground FUNCTION
DS4520
Block Diagram
DS4520
SDA SCL A0 A1 A2 VCC VCC I/O CONTROL (F2h-F3h) GND EEPROM 64 BYTES USER MEMORY [00h TO 3Fh] I/O STATUS (F8h-F9h) PULLUP ENABLE (F0h-F1h)
I2C INTERFACE
I/O CONTROL REGISTERS
I/O CELL (x9) VCC
RPU I/O_n [n = 0 TO 8]
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9-Bit I2C Nonvolatile I/O Expander Plus Memory DS4520
Detailed Description
The DS4520 contains nine bidirectional, NV, input/output (I/O) pins, and a 64-byte EEPROM user memory. The I/O pins and user memory are accessible through an I2C-compatible serial bus.
Slave Address and Address Pins
The DS4520's slave address is determined by the state of the A0, A1, and A2 address pins as shown in Figure 1. Address pins connected to GND result in a `0' in the corresponding bit position in the slave address. Conversely, address pins connected to VCC result in a `1' in the corresponding bit positions. I 2 C communication is described in detail in a later section.
Programmable NV I/O Pins
Each programmable I/O pin consists of an input and an open-collector output with a selectable internal pullup resistor. To enable the pullups for each I/O pin, write to the Pullup Enable Registers (F0h and F1h). To pull the output low or place the pulldown transistor into a highimpedance state, write to the I/O Control Registers (F2h and F3h). To read the voltage levels present on the I/O pins, read the I/O Status Registers (F8h and F9h). To determine the status of the output register, read the I/O Control Registers and the Pullup Resistor Registers. The I/O Control Registers and the Pullup Enable Registers are all SRAM shadowed EEPROM registers. It is possible to disable the EEPROM writes of the registers using the SEE bit in the Configuration Register. This reduces the time required to write to the register and increases the amount of times the I/O pins can be adjusted before the EEPROM is worn out.
I2C Serial Interface Description
I2C Definitions
The following terminology is commonly used to describe I2C data transfers. Master Device: The master device controls the slave devices on the bus. The master device generates SCL clock pulses, start, and stop conditions. Slave Devices: Slave devices send and receive data at the master's request. Bus Idle or Not Busy: Time between stop and start conditions when both SDA and SCL are inactive and in their logic-high states. When the bus is idle it often initiates a low-power mode for slave devices. Start Condition: A start condition is generated by the master to initiate a new data transfer with a slave. Transitioning SDA from high to low while SCL remains high generates a start condition. See the timing diagram for applicable timing. Stop Condition: A stop condition is generated by the master to end a data transfer with a slave. Transitioning SDA from low to high while SCL remains high generates a stop condition. See the timing diagram for applicable timing. Repeated Start Condition: The master can use a repeated start condition at the end of one data transfer to indicate that it immediately initiates a new data transfer following the current one. Repeated starts are commonly used during read operations to identify a specific memory address to begin a data transfer. A repeated start condition is issued identically to a normal start condition. See the timing diagram for applicable timing. Bit Write: Transitions of SDA must occur during the low state of SCL. The data on SDA must remain valid and unchanged during the entire high pulse of SCL plus the setup and hold time requirements (see Figure 2). Data is shifted into the device during the rising edge of the SCL.
Memory Map and Memory Types
The DS4520 memory map is shown in Table 1. Three different types of memory are present in the DS4520: EEPROM, SRAM shadowed EEPROM, and SRAM. Memory locations specified as EEPROM are NV. Writing to these locations results in an EEPROM write cycle for a time specified by tWR in the AC Electrical Characteristics table. Locations specified as SRAM shadowed EEPROM can be configured to operate in one of two modes specified by the SEE bit (the LSB of the Configuration Register, F4h). When the SEE bit = 0 (default), the memory location acts like EEPROM. However, when SEE = 1, shadow SRAM is written to instead of the EEPROM. This eliminates both the EEPROM write time, tRW, as well as the concern of wearing out the EEPROM. This is ideal for applications that wish to constantly write to the I/Os. Power-up default states can be programmed for the I/Os in EEPROM (with SEE = 0) and then once powered-up, SEE can be written to a 1 so the I/Os can be updated periodically in SRAM. The final type of memory present in the DS4520 is standard SRAM.
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9-Bit I2C Nonvolatile I/O Expander Plus Memory
Table 1. DS4520 Memory Map
ADDRESS 00h to 3Fh 40 to E7h E8 to EFh F0h F1h SRAM Shadowed EEPROM [EEPROM writes are disabled if the SEE bit = 1] TYPE EEPROM -- EEPROM NAME FUNCTION FACTORY DEFAULT 00h -- -- 00h 00h
DS4520
User Memory 64 bytes of general-purpose user EEPROM. Reserved Reserved Pullup Enable 0 Pullup Enable 1 Undefined address space for future expansion. Reads and writes to this space have no effect on the device. -- Pullup enable for I/O_0 to I/O_7. I/O_0 is the LSB and I/O_7 is the MSB. Set the corresponding bit to enable the pullup; clear the bit to disable the pullup. Pullup enable for I/O_8. I/O_8 is the LSB. Only the LSB is used. Set the LSB bit to enable the pullup on I/O_8; clear the LSB to disable the pullup. I/O control for I/O_0 to I/O_7. I/O_0 is the LSB and I/O_7 is the MSB. Clearing the corresponding bit of the register pulls the selected I/O pin low; setting the bit places the pulldown transistor into a high-impedance state. When the pulldown is high impedance, the output floats if no pullup/down is connected to the pin. I/O control for I/O_8. I/O_8 is the LSB. Only the LSB is used. Clearing the LSB of the register pulls the I/O_8 pin low; setting the LSB places the pulldown transistor into a high-impedance state. When the pulldown is high impedance, the output floats if no pullup/down is connected to the pin.
F2h
I/O Control 0
FFh
F3h
I/O Control 1
01h
F4h F5h to F7h F8h SRAM F9h FAh to FFh
Configuration register. The LSB is the SEE bit. When set, this bit disables Configuration writes to the EEPROM; writing only affects the shadow SRAM. When set to 0, both the EEPROM and the shadow SRAM is written. User Memory 3 bytes of general-purpose user EEPROM. I/O Status 0 I/O status for I/O_0 to I/O_7. I/O_0 is the LSB and I/O_7 is the MSB. Writing to this register has no effect. Read this register to determine the state of the I/O_0 to I/O_7 pins. I/O status for I/O_8. I/O_8 is the LSB. Only the LSB is used; the other bits could be any value when read. Writing to this register has no effect. Read this register to determine the state of the I/O_8 pin. 6 bytes of general-purpose SRAM.
00h 00h
--
I/O Status 1 SRAM User
MSB 1 0 1 0 A2 A1 A0
LSB R/W
SLAVE ADDRESS* *THE SLAVE ADDRESS IS DETERMINED BY ADDRESS PINS A0, A1, AND A2.
READ/WRITE BIT
Figure 1. DS4520 Slave Address Byte _____________________________________________________________________ 7
9-Bit I2C Nonvolatile I/O Expander Plus Memory
Bit Read: At the end a write operation, the master must release the SDA bus line for the proper amount of setup time before the next rising edge of SCL during a bit read (see Figure 2). The device shifts out each bit of data on SDA at the falling edge of the previous SCL pulse and the data bit is valid at the rising edge of the current SCL pulse. Remember that the master generates all SCL clock pulses including when it is reading bits from the slave. Acknowledgement (ACK and NACK): An acknowledgement (ACK) or not acknowledge (NACK) is always the 9th bit transmitted during a byte transfer. The device receiving data (the master during a read or the slave during a write operation) performs an ACK by transmitting a zero during the 9th bit. A device performs a NACK by transmitting a one during the 9th bit. Timing (Figure 2) for the ACK and NACK is identical to all other bit writes. An ACK is the acknowledgement that the device is properly receiving data. A NACK is used to terminate a read sequence or as an indication that the device is not receiving data. Byte Write: A byte write consists of 8 bits of information transferred from the master to the slave (most significant bit first) plus a 1-bit acknowledgement from the slave to the master. The 8 bits transmitted by the master are done according to the bit write definition and the acknowledgement is read using the bit read definition. Byte Read: A byte read is an 8-bit information transfer from the slave to the master plus a 1-bit ACK or NACK from the master to the slave. The 8 bits of information that are transferred (most significant bit first) from the slave to the master are read by the master using the bit read definition above, and the master transmits an ACK using the bit write definition to receive additional data bytes. The master must NACK the last byte read to terminated communication so the slave returns control of SDA to the master. Slave Address Byte: Each slave on the I 2 C bus responds to a slave address byte sent immediately following a start condition. The slave address byte contains the slave address in the most significant 7 bits and the R/W bit in the least significant bit. The DS4520's slave address is determined by the state of the A0, A1, and A2 address pins as shown in Figure 1. Address pins connected to GND result in a `0' in the corresponding bit position in the slave address. Conversely, address pins connected to VCC result in a `1' in the corresponding bit positions. When the R/W bit is 0 (such as in A0h), the master is indicating it will write data to the slave. If R/W = 1, (A1h in this case), the master is indicating it will read from the slave.
DS4520
SDA tBUF tHD:STA tLOW SCL tHD:STA STOP START tHD:DAT NOTE: TIMING IS REFERENCED TO VIL(MAX) AND VIH(MIN) tHIGH tSU:DAT REPEATED START tSU:STA tSU:STO tR tF
tSP
Figure 2. I2C Timing Diagram
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9-Bit I2C Nonvolatile I/O Expander Plus Memory
If an incorrect slave address is written, the DS4520 assumes the master is communicating with another I2C device and ignores the communication until the next start condition is sent. Memory Address: During an I2C write operation, the master must transmit a memory address to identify the memory location where the slave is to store the data. The memory address is always the second byte transmitted during a write operation following the slave address byte. Acknowledge Polling: Any time an EEPROM page is written, the DS4520 requires the EEPROM write time (tW) after the stop condition to write the contents of the page to EEPROM. During the EEPROM write time, the device does not acknowledge its slave address because it is busy. It is possible to take advantage of this phenomenon by repeatedly addressing the DS4520, which allows communication to continue as soon as the device is ready. The alternative to acknowledge polling is to wait for a maximum period of tW to elapse before attempting to access the device. EEPROM Write Cycles: When EEPROM writes occur, the DS4520 writes the whole EEPROM memory page even if only a single byte on a page was modified. Writes that do not modify all 8 bytes on the page are valid and do not corrupt any other bytes on the same page. Because the whole page is written, even bytes on the page that were not modified during the transaction are still subject to a write cycle. The DS4520's EEPROM write cycles are specified in the Nonvolatile Memory Characteristics table. The specification shown is at the worst-case temperature. It is capable of handling approximately 10x that many writes at room temperature. Reading a Single Byte from a Slave: Unlike the write operation that uses the specified memory address byte to define where the data is to be written, the read operation occurs at the present value of the memory address counter. To read a single byte from the slave, the master generates a start condition, writes the slave address byte with R/W = 1, reads the data byte with a NACK to indicate the end of the transfer, and generates a stop condition. However, since requiring the master to keep track of the memory address counter is impractical, the following method should be used to perform reads from a specified memory location. Manipulating the Address Counter for Reads: A dummy write cycle can be used to force the address counter to a particular value. To do this the master generates a start condition, writes the slave address byte (R/W = 0), writes the memory address where it desires to read, generates a repeated start condition, writes the slave address byte (R/W = 1), reads data with ACK or NACK as applicable, and generates a stop condition.
DS4520
I2C Communication
Writing a Single Byte to a Slave: The master must generate a start condition, write the slave address byte (R/W = 0), write the memory address, write the byte of data, and generate a stop condition. Remember the master must read the slave's acknowledgement during all byte write operations. Writing Multiple Bytes to a Slave: To write multiple bytes to a slave, the master generates a start condition, writes the slave address byte (R/W = 0), writes the memory address, writes up to 8 data bytes, and generates a stop condition. The DS4520 is capable of writing up to 8 bytes (one page or row) with a single write transaction. This is internally controlled by an address counter that allows data to be written to consecutive addresses without transmitting a memory address before each data byte is sent. The address counter limits the write to one 8byte page. Attempts to write to additional pages of memory without sending a stop condition between pages results in the address counter wrapping around to the beginning of the present row. The first row begins at address 00h and subsequent rows begin at multiples of 8 there on (08h, 10h, 18h, 20h, etc). To prevent address wrapping from occurring, the master must send a stop condition at the end of the page, and then wait for the bus free or EEPROM write time to elapse. Then the master can generate a new start condition, write the slave address byte (R/W = 0), and the first memory address of the next memory row before continuing to write data.
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9-Bit I2C Nonvolatile I/O Expander Plus Memory DS4520
TYPICAL I2C WRITE TRANSACTION MSB START 1 0 1 0 A2 A1 LSB A0 R/W SLAVE ACK MSB b7 b6 b5 b4 b3 b2 b1 LSB b0 SLAVE ACK MSB b7 b6 b5 b4 b3 b2 b1 LSB b0 SLAVE ACK STOP
SLAVE ADDRESS*
READ/ WRITE
REGISTER ADDRESS
DATA
*THE SLAVE ADDRESS IS DETERMINED BY ADDRESS PINS A0, A1, AND A2.
EXAMPLE I2C TRANSACTIONS (WHEN A0, A1, AND A2 ARE CONNECTED TO GND) A0h A) SINGLE BYTE WRITE -WRITE I/O CONTROL 0 REGISTER TO 00h B) SINGLE BYTE READ -READ I/O STATUS 0 RESISTER F2h SLAVE 0 0 0 0 0 0 0 0 ACK SLAVE ACK A1h REPEATED START FFh SLAVE ACK 111 1 1 1 1 1 SLAVE ACK STOP 1 0 1 0 0 0 0 1 SLAVE ACK STOP
START 1 0 1 0 0 0 0 0 SLAVE 1 1 1 1 0 0 1 0 ACK A0h F8h
DATA I/O STATUS MASTER NACK STOP
START 1 0 1 0 0 0 0 0 SLAVE 1 1 1 1 1 0 0 0 SLAVE ACK ACK A0h F0h SLAVE ACK 11110 000
C) SINGLE BYTE WRITE -WRITE PULLUP ENABLE 0 REGISTER TO FFh
START 1 0 1 0 0 0 0 0
A0h D) TWO BYTE WRITE -WRITE I/O CONTROL 0 AND I/O CONTROL 1 REGISTERS TO 00h
F2h
00h 00000000 SLAVE ACK
00h 00000000 SLAVE ACK DATA I/O STATUS 0 MASTER ACK STOP
SLAVE SLAVE START 1 0 1 0 0 0 0 0 11110 010 ACK ACK A0h F8h SLAVE SLAVE 111 11000 ACK ACK
D) TWO BYTE READ -READ I/O STATUS 0 AND I/O STATUS 1 RGISTERS
START 1 0 1 0 0 0 0 0
REPEATED START
A1h 1 0 1 0 0 0 0 1 SLAVE ACK
DATA I/O STATUS 1 MASTER NACK STOP
Figure 3. I2C Communication Examples
See Figure 3 for a read example using the repeated start condition to specify the starting memory location. Reading Multiple Bytes from a Slave: The read operation can be used to read multiple bytes with a single transfer. When reading bytes from the slave, the master simply ACKs the data byte if it desires to read another byte before terminating the transaction. After the master reads the last byte it must NACK to indicate the end of the transfer and generates a stop condition.
Chip Topology
TRANSISTOR COUNT: 14,398 SUBSTRATE CONNECTED TO GROUND
Applications Information
Power-Supply Decoupling
To achieve best results, it is highly recommended that a decoupling capacitor is used on the IC power-supply pins. Typical values of decoupling capacitors are 0.01F and 0.1F. Use a high-quality, ceramic, surface-mount capacitor, and mount it as close as possible to the VCC and GND pins of the IC to minimize lead inductance.
Package Information
For the latest package outline information, go to www.maxim-ic.com/DallasPackInfo.
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
10 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2004 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.
is a registered trademark of Dallas Semiconductor Corporation.

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